Static RAM Interfacing

The semiconductor RAM are broadly two types – static RAM and dynamic RAM.  The semiconductor memories are organised as two dimensional arrays of memory locations.  For example 4K * 8 or 4K byte memory contains 4096 locations, where each locations contains 8-bit data and only one of the 4096 locations can be selected at a time. Once a location is selected all the bits in it are accessible using a group of conductors called Data bus.  For addressing the 4K bytes of memory, 12 address lines are required.


In general to address a memory location out of N memory locations, we will require at least n bits of address, i.e. n address lines where n = Log2 N. Thus if the microprocessor has an address lines, then it is able to address at the most N locations of memory, where 2 n=N. If out of N locations only P memory locations are to be interfaced, then the least significant p address lines out of the available n lines can be directly connected from the microprocessor to the memory chip while the remaining (n-p) higher order address lines may be used for address decoding as inputs to the chip selection logic.

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Concluding Remark

The memory address depends upon the hardware circuit used for decoding the chip select (CS). The output of the decoding circuit is connected with the CS pin of the memory chip. The general procedure of static memory interfacing with 8086 is briefly described as follows: 1. Arrange the available memory chip so as to obtain 16- bit data bus width. The upper 8-bit bank is called as odd address memory bank and the lower 8-bit bank is called as even address memory bank.

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