Interrupt Sequence in an 8086 system

The Interrupt sequence in an 8086-8259A system is described as follows: One or more IR lines are raised high that set corresponding IRR bits. 8259A resolves priority and sends an INT signal to CPU. The CPU acknowledge with INTA pulse. Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A does not drive data during this period.

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Interrupt cycle

The 8086 will initiate a second INTA pulse. During this period 8259A releases an 8-bit pointer on to a data bus from where it is read by the CPU. This completes the interrupt cycle. The ISR bit is reset at the end of the second INTA pulse if automatic end of interrupt (AEOI) mode is programmed. Otherwise ISR bit remains set until an appropriate EOI command is issued at the end of interrupt subroutine.

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Concluding remark

The command words of 8259A are classified in two groups Initialization command words (ICW) and. Operation command words (OCW). Initialization Command Words (ICW): Before it starts functioning, the 8259A must be initialized by writing two to four command words into the respective command word registers. These are called as initialized command words.

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