Architecture and Signal Descriptions of 8259A

The architectural block diagram of 8259A is shown in fig1. The functional explication of each block is given in the following text in brief.

Interrupt Request Register (RR)

The interrupts at IRQ input lines are handled by Interrupt Request internally. IRR stores all the interrupt request in it in order to serve them one by one on the priority basis.

In-Service Register (ISR)

This stores all the interrupt requests those are being served, i.e. ISR keeps a track of the requests being served.

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Priority Resolver

This unit determines the priorities of the interrupt requests appearing simultaneously. The highest priority is selected and stored into the corresponding bit of ISR during INTA pulse. The IR 0 has the highest priority while the IR 7 has the lowest one, normally in fixed priority mode. The priorities however may be altered by programming the 8259A in rotating priority mode.

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Interrupt Mask Register (IMR)

This register stores the bits required to mask the interrupt inputs. IMR operates on IRR at the direction of the Priority Resolver.

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Interrupt Control Logic

This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the data bus.

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